1. Field of the Invention
The present invention relates to a floating gate type non-volatile semiconductor memory device in which data is rewritten by injecting or extracting carriers into or from a floating gate.
2. Description of the Related Art
FIGS. 1A to 1C show an N-channel type flash EEPROM according to a related art. In this related art, an SiO.sub.2 film 12 is formed on the surface of an isolation region of a P-type Si substrate 11, and an SiO.sub.2 film 13 is formed as a gate oxide film on the surface of an active region surrounded by the SiO.sub.2 film 12. A polysilicon film 14 on the SiO.sub.2 films 13 and 12 forms a floating gate which is isolated for every memory cell.
An SiO.sub.2 film 15 on the polysilicon film 14 forms a capacitor coupling insulating film, and a polysilicon film 16 on the SiO.sub.2 films 15 and 12 forms a control gate for continuous memory cells in the row direction. N-type source and drain diffusion layers 17s and 17d are formed in the active region on both the sides of the polysilicon films 14 and 16. The active region below the polysilicon films 14 and 16 serves as a channel region 18.
An overlapping portion between the drain diffusion layer 17d and the polysilicon film 14 serves as a tunnel region 22 for flowing a tunnel current 21 through the SiO.sub.2 film 13 at this portion. A contact hole 23 for a bit line (not shown) is formed in an interlayer insulator (not shown) covering the entire surface on the Si substrate 11, and the like, and reaches the drain diffusion layer 17d.
In this related art, when electrons are to be extracted from the polysilicon film 14 serving as the floating gate to the drain diffusion layer 17d so as to rewrite data, a high voltage of about 15 to 20 V with respect to the polysilicon film 16 serving as the control gate is applied to the drain diffusion layer 17d, and a high electric field of 10 MV/cm or more is applied to the SiO.sub.2 film 13 to generate the tunnel current 21 in the SiO.sub.2 film 13 in the tunnel region 22. Note that electrons may also be extracted to the source diffusion layer 17s.
When a voltage as high as about 15 to 20 V with respect to the polysilicon film 16 is applied to the drain diffusion layer 17d, however, as shown in FIG. 1C, a depletion layer 25 is formed on both the sides of a junction 24 between the drain diffusion layer 17d and the Si substrate 11 and near the boundary between the drain diffusion layer 17d and the polysilicon film 14, i.e., near the tunnel region 22. At the same time, a P-type parasitic inversion layer 26 is formed from the tunnel region 22 to the channel region 18 in contact with the Si substrate 11.
On the other hand, band to band transition very easily occurs in the tunnel region 22 upon application of the above-described high voltage to generate a large number of electron-hole pairs. The generated electrons flow into the drain diffusion layer 17d due to an electric field in the depletion layer 25, while the holes flow into the Si substrate 11 through the parasitic inversion layer 26.
As a result, a band to band current as large as about 0.1 to 1 .mu.A flows between the drain diffusion layer 17d and the Si substrate 11 and is measured as a substrate current. Therefore, in the related art shown in FIGS. 1A to 1C, a high-voltage, large-current power supply is required in addition to a normal voltage power supply, resulting in a complicated arrangement.
In a method employed to suppress the above-described band to band current, the impurity concentration of the drain diffusion layer 17d is set not so high. By this method, however, not only the band to band current but also an electron flow from the polysilicon film 14 to the drain diffusion layer 17d are suppressed, resulting in an increase in data rewrite time and a rewrite error.